With semiconductor devices, in particular with memory devices such as DRAMS (DRAM=Dynamic Random Access Memory or dynamic read-write memory, respectively)—based e.g. on CMOS technology—so-called clock signals are used for coordinating the processing or advancing, respectively, of the data with respect to time.
In the case of conventional semiconductor devices, an individual clock signal—that is applied at an individual line—is, in general, used (i.e. a so-called “single-ended” clock signal).
The data may then be advanced e.g. at the rising clock edge of the individual clock signal (or, alternatively, e.g. at the falling clock edge of the individual clock signal).
Furthermore, so called DDR devices, in particular DDR-DRAMs (DDR-DRAM=Double Data Rate-DRAM or DRAM with double data rate, respectively), are already known in prior art.
In the case of DDR devices—instead of one individual clock signal applied at an individual line (“single-ended clock signal)—two differential, oppositely-inverse clock signals applied on two separate lines are used.
Whenever e.g. the first clock signal of the two clock signals changes from a state “logically high” (e.g. a high voltage level) to a state “logically low” (e.g. a low voltage level), the second clock signal changes—substantially simultaneously—its state from “logically low” to “logically high” (e.g. from a low to a high voltage level).
Vice versa, whenever the first clock signal changes from a state “logically low” (e.g. a low voltage level) to a state “logically high” (e.g. a high voltage level), the second clock signal (again substantially simultaneously) changes its state from “logically high” to “logically low” (e.g. from a high voltage level to a low voltage level).
In DDR devices, the data are, in general, advanced both at the rising edge of the first clock signal and at the rising edge of the second clock signal (or both at the falling edge of the first clock signal and at the falling edge of the second clock signal, respectively).
Thus, advancing of the data in a DDR device is performed more frequently or more quickly, respectively (in particular twice as frequent or twice as quick, respectively) than with corresponding, conventional devices with an individual or “single-ended” clock signal, i.e., the data rate is higher, in particular twice as high, as with corresponding, conventional devices.
The clock signal used—internally—in the device for coordinating the processing or advancing, respectively, of the data with respect to time (“DQS signal or “data strobe” signal, respectively) (or—when differential, oppositely-inverse clock signals are used—the internal clock signal DQS and the clock signal BDQS that is oppositely-inverse to the clock signal DQS) must be synchronous to a clock signal (“CLK signal or “clock” signal, respectively) input externally into the device (or synchronous to the differential clock signals CLK, BCLK input externally into the device, respectively).
The external clock signal(s) CLK, BCLK is/are generated by an appropriate clock signal generator connected with the device.
For synchronizing the internally generated clock signal DQS or the internally generated clock signals DQS, BDQS, respectively, with the external clock signal(s) CLK, BCLK, a clock signal synchronizing device, e.g. a DLL circuit (DLL=Delay-Locked-Loop) is used. Such a circuit is, for instance, known from EP 964 517.
A clock signal synchronizing device may, for instance, include a first delay module into which the external clock signal(s) CLK, BCLK is/are input, and which charges the input external clock signal(s) CLK, BCLK—as a function of a control signal output by a phase comparator—with a variable control time tvar that is adjustable by the control signal.
The signal(s) output by the first delay module may be used—internally—in the device for coordinating the processing or advancing, respectively, of the data with respect to time (i.e. as—internal—clock signal(s) DQS or BDQS, respectively).
The signal DQS output by the first delay module is supplied to a second delay module that charges the input signal DQS with a—fixed—delay time tconst corresponding approximately to the sum of the signal delays caused by the receiver(s) (“receiver delay”), the respective data path (“data path delay”), and the off-chip driver(s) (“OCD delay”).
The signal output by the second delay module (FB signal or “feedback signal”, respectively) is supplied to the above-mentioned phase comparator; there, the phasing of the FB signal is compared to that of the CLK signal that has also been input into the phase comparator. Depending on whether the phase of the FB signal hurries ahead or runs after that of the CLK signal, the phase comparator outputs—as a control signal for the above-mentioned first delay module—an incrementing signal (INC signal) or a decrementing signal (DEC signal), which result in that the delay tvar of the CLK signal effected by the first delay module is—in the case of an INC signal—increased, or—in the case of a DEC signal—decreased, so that the CLK signal and the FB signal are finally synchronized, i.e. the clock signal synchronizing device is “locked”.
In the locked state of the clock signal synchronizing device, a filter—connected between the phase comparator and the first delay module—may be activated, which forwards the INC or DEC signal to the first signal delay module only when for a particular number of successive clocks—e.g. defined by the clock signals CLK, BCLK—(e.g. 16 successive clocks) one and the same signal is output by the phase comparator (e.g. for 16 successive clocks an INC signal, or for 16 successive clocks a DEC signal).
By that—in the locked state of the clock signal synchronizing device—jitter in the clock signal DQS output by the clock signal synchronizing device may be avoided, while—from time to time (namely, when the INC or DEC signal is forwarded from the filter to the first signal delay module)—resynchronizing of the clock signal DQS with respect to the clock signal CLK can nevertheless be ensured.
However, e.g. when—during the locked state of the clock signal synchronizing device—the frequency of the CLK signal changes, it may take a relatively long time until the CLK signal and the DQS signal are synchronized again.